Title:
DISCRETE TIME SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JP3451117
Kind Code:
B2
Abstract:
PURPOSE: To provide a discrete time signal processor which can obtain a clock signal having a desired frequency to begin with a single stable oscillator frequency and does not have the ratio of the oscillation frequency and clock frequency limited to a positive integer.
CONSTITUTION: A switchable frequency divider 7 which is driven by a Σ-Δ modulator 9 is used. An effective divisor (m) of n≤m≤n+1 is actualized by alternation from one divisor (n) to the other divisor n+1 or vice versa and very precise frequency tuning is therefore possibly caused. The use of the Σ-Δ modulator 9 gives the advantage that the frequency spectrum of a sampled signal is not disturbed by the frequency spectrum of a sampling signal (clock signal) generated by the switchable frequency divider 7.
Inventors:
Dieter Ernesto Mitchell Terssen
Application Number:
JP28129293A
Publication Date:
September 29, 2003
Filing Date:
November 10, 1993
Export Citation:
Assignee:
Konin Krekka Philips Electronics NV
International Classes:
G11C27/02; H04L7/00; H04B14/04; (IPC1-7): H04L7/00; H04B14/04
Domestic Patent References:
| JP1115222A | ||||
| JP1288016A | ||||
| JP376318A | ||||
| JP63252016A | ||||
| JP54128253A | ||||
| JP62216421A |
Attorney, Agent or Firm:
Kosugi Sugimura (4 others)
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