PURPOSE: To automatically regenerate a display clock by providing a PLL circuit with a means which makes a comparison with the phase of a regenerated clock signal and a means which automatically sets the frequency division ratio of the regenerated clock signal with its output signal.

CONSTITUTION: The image signal of a display signal is a binary signal and a phase comparing means 5 makes a phase comparison between a change point (edge) of the level of the image signal and the output signal of a VCO and a comparison with the phase of the leading edge of the regenerated clock and outputs no signal when the phase difference is always 0 or constant, but outputs a detection signal when the phase difference between them varies. Frequency division ratio automatic setting means 4 and 9 when inputting the detection signal properly varies the set value of a frequency division ratio until the detection signal is ceased. Consequently, the frequency of the minimum unit of a display of the image signal automatically matches the frequency of the output signal of the VCO, so even if the frequency ratio of a dot clock and the synchronizing signal of the display signal varies, the frequency division ratio of a frequency divider 4 automatically matches. Consequently, the display clock of specific frequency can automatically be generated.