Title:
歪み軽減量子化器回路、歪み雑音を軽減する方法及びデジタル送信機
Document Type and Number:
Japanese Patent JP6854915
Kind Code:
B2
Abstract:
A distortion mitigation quantizer circuit includes a pre-quantizer to generate a first quantized signal having L output signal levels from an input signal and a digital pulse-width-modulation (PWM) circuit to modulate the first quantized signal using M modulating carriers with PWM carrier frequency fp and according to an over sampling ratio (OSR) N in order to generate a second quantized signal. In this case, a number of the modulating carriers M is substantially equal to twice L/N.
Inventors:
Marui
Tanovic, Omar
Tanovic, Omar
Application Number:
JP2019553123A
Publication Date:
April 07, 2021
Filing Date:
January 30, 2018
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H03K7/08; H04B1/04
Domestic Patent References:
| JP2013255003A | ||||
| JP7298604A | ||||
| JP2016217908A | ||||
| JP2003061362A | ||||
| JP2016530739A | ||||
| JP2001503210A | ||||
| JP2001127562A | ||||
| JP2004336703A |
Foreign References:
| US20110064245 |
Attorney, Agent or Firm:
Michiharu Soga
Kajinami order
Kazuhiro Oyaku
Shunichi Ueda
Junichiro Yoshida
Kajinami order
Kazuhiro Oyaku
Shunichi Ueda
Junichiro Yoshida