Title:
DIVIDER
Document Type and Number:
Japanese Patent JPH05327482
Kind Code:
A
Abstract:
PURPOSE: To secure the stable division output regardless of the frequency of an original pulse signal with a circuit which divides an original pulse signal CK.
CONSTITUTION: A counter 10 is provided to count the number of pulses of an original pulse signal together with an AND gate G1 which outputs a logic signal when the output of the counter 10 is equal to the count value corresponding to a prescribed dividing ratio, a signal inverting circuit 11 which inverts the output with each reception of the logic signal, and a shift register 12 which delays the output signal GO1 of the gate G1 based on the cycle of an original pulse signal CK. Then the delayed output FO6 is used as a reset signal of the counter 10.
Inventors:
ISHII TOSHIHIKO
Application Number:
JP14868292A
Publication Date:
December 10, 1993
Filing Date:
May 14, 1992
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H03K21/40; H03K23/00; (IPC1-7): H03K23/00; H03K21/40
Attorney, Agent or Firm:
Kenichi Hayase