To enhance efficiency of transferring data by dynamically controlling DMA (Direct Memory Access) transfer.

A DMA transfer control device is configured of a DMA arbiter for performing DMA transfer for each DMA channel from the combination of a memory and a plurality of input/output devices and a DMA control circuit for controlling the DMA arbiter, and provided with a determination part 11; and a transfer time calculation part 12 for calculating the next DMA transfer scheduled time based on a DMA transfer size and a determined time accompanied by a DMA transfer request. This DMA transfer control device includes: a timer counter 13 for measuring the determined time with a unit time interval; a comparator 10 for comparing the determined time when the DMA transfer request arrives with the DMA transfer scheduled time. When the output of the comparator 10 shows that the determined time is the DMA transfer scheduled time and following time, the determination part 11 transmits it as DMA transfer permission to the DMA arbiter.