To prevent the incomplete phase adjustment that is caused by the jitters of the receiving data or the phases of the receiving data and receiving clocks.

A DPLL circuit counts the source clocks (× 16CLK) to generate receiving clocks, sets a signal DLY or FWD showing the phase delay or advance when the count value shows 8 to 15 or 1 to 7 at the time of detection of a receiving data changing point, and increases or decreases the full count number 16 of a counter by 1 or 2 to adjust the phases of the receiving clocks. In such a constitution, a means is added to set the delayed signal DLYLAT or FWDLAT of the signal DLY or FWD when the count value shows 8 to 10 or 5 to 7 respectively and to inhibit the signals FWD and FWDLAT via the signal DLYLAT and also to inhibit the signals DLY and DLYLAT via the signal FWDLAT respectively. Thus it is evaded to alternately repeat the plus and minus phase adjustment of the receiving clocks as long as the difference of these clock phases is large.