Title:
DRIVE CIRCUIT OF DISPLAY DEVICE
Document Type and Number:
Japanese Patent JP2006098764
Kind Code:
A
Abstract:
To avoid a case in which voltage does not pass between a source and a drain of a MOS transistor when a MOS transistor either of an n channel or a p channel is used in a drive circuit.
High integration is attained by forming the MOS transistors T, T' arranged at an input stage or an output stage of each shift register SR by either of the n channel or the p channel and voltage of control signals UD1, reverse control signals/UD1 applied to gates of each of the MOS transistors T, T' are set to voltage different from voltage of a pulse signal ST applied to the sources or the drains. Thus, the voltage is made to surely pass between the sources and the drains of each of the MOS transistors T, T'.
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Inventors:
TSUNASHIMA TAKANORI
Application Number:
JP2004285120A
Publication Date:
April 13, 2006
Filing Date:
September 29, 2004
Export Citation:
Assignee:
TOSHIBA MATSUSHITA DISPLAY TEC
International Classes:
G09G3/36; G02F1/133; G09G3/20; G11C19/00
Attorney, Agent or Firm:
Hidekazu Miyoshi
Iwa Saki Kokuni
Kawamata Sumio
Nakamura Tomoyuki
Masakazu Ito
Shunichi Takahashi
Toshio Takamatsu
Iwa Saki Kokuni
Kawamata Sumio
Nakamura Tomoyuki
Masakazu Ito
Shunichi Takahashi
Toshio Takamatsu