To prevent the damage of an LCD at the time of the changeover of the power saving mode ON/OFF of a power saving power supply circuit.

The controller is provided with an FET 84 interposed in the driving voltage line of the LCD to which the control voltage (+5 V) and driving voltage (+24 V) of the power saving power supply circuit 10 are applied when a power saving mode is OFF and a standby voltage (+5 VE) is applied when the power saving mode is ON. The controller is also provided with timing control means 80-86 to be conductive after the rise of the control voltage of the FET 84 at the time of shifting to the power saving mode OFF and to be non-conductive at the time of the fall of the control voltage of the FET 84 at the time of shifting to the power saving mode ON. The control means 80-86 are provided with FFs 81 and 82 for turning the FET 84 ON in response to display timing signals FM generated by the LCD at the time of shifting to the power saving mode OFF. The conductive resistance of the FET 84 is 10 Ωor less.