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Title:
DUAL PROCESSOR DEVICE
Document Type and Number:
Japanese Patent JPH06230995
Kind Code:
A
Abstract:

PURPOSE: To simplify constitution for dual switching control and improve the reliability by performing both transfer processing of transmission/reception and communication processing for data between programs through an operating system.

CONSTITUTION: Through the queuing means 17 on a stand-by side processor device MD2, program execution memory means 12 in mutual processor devices write data in an addresses designated by their own memories each time an application program calls the OS. Then the same addresses of the memories in the other party's processor devices are checked and waiting is made until some data is written from the control-side processor device MD1. Once it is confirmed that some data is written, the data in the memory means 12 in the other party's processor device are cleared and the waiting is made till the clearing of the data in its own memory means 12. The queuing means 17 of the control-side processor device MD1 performs similar processing.


Inventors:
HAZAMA RIYUU
ITO HIROKI
AKAI SO
MATSUDA TOSHIHIKO
Application Number:
JP1374893A
Publication Date:
August 19, 1994
Filing Date:
January 29, 1993
Export Citation:
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Assignee:
YOKOGAWA ELECTRIC CORP
International Classes:
G06F11/20; G06F11/18; (IPC1-7): G06F11/20
Attorney, Agent or Firm:
Shinsuke Ozawa