PURPOSE: To test a refreshing function precisely and rapidly by incorporating an internal address generating circuit and a logical circuit receiving a refresh control signal and a prescribed control signal and executing writing operation under a refresh cycle in the titled RAM.

CONSTITUTION: Logical "0" is previously written in all bit. When a refresh singal REF is kept at a low level, a counter circuit is advanced in accordance with a timing signal actuating a timer circuit, so that internal address signals ax0W axi are updated. If a write enable signal WE is turned to the low level and logical "1" is written in a data input terminal simultaneously, the storage information of a specific memory cell is rewritten from "0" to "1". Whether address advance for refresh operation is normally executed or not can be tested by checking said rewriting from its reading operation.