Title:
ECHO SUPPRESSION SYSTEM
Document Type and Number:
Japanese Patent JPH05183474
Kind Code:
A
Abstract:
PURPOSE: To effectively eliminate ghosts and echoes by performing composition from many filter taps and programmable delay lines and specifying a position as a constitution part by program control. CONSTITUTION: The echo elimination filter circuit 200 of an integrated circuit is and FIR type (finite length impulse response) and IIR type (infinite length impulse response) filter section. A coefficient calculated in a processor 25 is cyclically reloaded and algorithm for finding the coefficient is stored in a memory 155 and functions as a part of the processor 25. The processor 25 supplies a control word for assembling the circuit 200 and making it function and also receives clock signals from a PLL 158 and synchronization data from a circuit 160. The memory 155 stores ghost elimination reference signals during coefficient calculation and unprocessed elimination reference signals appearing at the output point of the circuit 200 are made to cyclically bypass the circuit 200 and utilized by the processor 25. The output of the circuit 200 is supplied through a D/A 35 to an LPF 156.
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Inventors:
KUREIGU BURATSUDORII GURIINBAA
Application Number:
JP13682692A
Publication Date:
July 23, 1993
Filing Date:
May 28, 1992
Export Citation:
Assignee:
PHILIPS NV
International Classes:
H04B3/20; H03H17/02; H04B3/23; H04N5/21; (IPC1-7): H04B3/20; H04B3/23; H04N5/21
Attorney, Agent or Firm:
Akihide Sugimura (5 outside)