Title:
ELECTRICAL INTERCONNECT STRUCTURE FOR EMBEDDED SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP2016046523
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide an electrical interconnect structure for an embedded semiconductor device package.SOLUTION: An electronic circuit package includes a first dielectric substrate having a first plurality of vias formed through a thickness thereof, a metalized contact layer coupled to a top surface of the first dielectric substrate, and a first die positioned within a first die opening formed through the thickness of the first dielectric substrate. Metalized interconnects are formed on a bottom surface of the first dielectric substrate and extend through the first plurality of vias to contact the metalized contact layer. A second dielectric substrate is coupled to the first dielectric substrate and has a second plurality of vias formed through a thickness thereof. Metalized interconnects extend through the second plurality of vias to contact the first plurality of metalized interconnects and contact pads of the first die. A first conductive element electrically couples the first die to the metalized contact layer.SELECTED DRAWING: Figure 18
Inventors:
MCCONNELEE PAUL ALAN
ARUN VIRUPAKSHA GOWDA
ARUN VIRUPAKSHA GOWDA
Application Number:
JP2015160009A
Publication Date:
April 04, 2016
Filing Date:
August 14, 2015
Export Citation:
Assignee:
GENERAL ELECTRIC CO GE
International Classes:
H01L23/12; H01L25/04; H01L25/18
Attorney, Agent or Firm:
Arakawa Satoshi
Hirokazu Ogura
Toshihisa Kurokawa
Takuto Tanaka
Hirokazu Ogura
Toshihisa Kurokawa
Takuto Tanaka