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Title:
EMITTER COUPLED LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JPH024015
Kind Code:
A
Abstract:

PURPOSE: To cause a switching speed to be high-speed by connecting the collector of a transistor in a signal basic cell to compose plural current switches, respectively, in the signal basic cell.

CONSTITUTION: In a basic cell 10B, the respective collectors of transistors Q1B and Q2B are connected by a first layer wiring 22. To respective terminals 11b and 12b, a reference voltage VBB is impressed, and an AND X.Y of signals X and Y inputted to the terminals 11a and 12a, respectively, is outputted through a transistor Q3B of an emitter follower from a terminal 13b. In such a way, since a collector connecting point is executed by the first layer wiring 22 in the basic cell 10B and the wiring 22 is sufficient by the degree of approximately 1/2 in comparison with a conventional case, the collector wiring capacities of the transistors Q1B and Q2B is are made small, and the switching speed can be made high-speed.


Inventors:
KADOI HIROYUKI
SUGIYAMA EIJI
ANDO NAOYUKI
TANDO YASUHIKO
SETO CHIKAHIRO
Application Number:
JP15109388A
Publication Date:
January 09, 1990
Filing Date:
June 21, 1988
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L27/118; H01L21/82; H03K19/086; H03K19/173; (IPC1-7): H01L21/82; H01L27/118; H03K19/086; H03K19/173
Domestic Patent References:
JPS61248619A1986-11-05
JPS48100066A1973-12-18
JPS5378160A1978-07-11
JPS61121612A1986-06-09
Attorney, Agent or Firm:
Tadahiko Ito (2 outside)



 
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