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Title:
EPITAXIAL WAFER AND LIGHT-EMITTING DIODE
Document Type and Number:
Japanese Patent JPH11186591
Kind Code:
A
Abstract:

To prevent characteristics failures caused by the occurrence of a zigzag type junction by a method wherein, in an epitaxial growth layer forming a p-n junction, silicon and tellurium and doped and telluric concentration near the p-n junction is set to a specified value.

In a method for continuously growing a p-n junction in a GaAs or GaAlAs epitaxial layer, in addition to silicon as a first dopant, tellurium is added as a second dopant to form the epitaxial layer on a GaAs substrate. Tellurium concentration near the p-n junction of the GaAs or GaAlAs epitaxial layer is set in a range of 3×1015 cm-3 to 1×1017 cm-3. Tellurium acts an n-type unipolar dopant and silicon which indicates p-type has concentration higher than silicon indicating an n-type near the p-n junction, and the formation of a zigzag type junction is prevented, the satisfactory p-n junction is formed, and the occurrence of element failure is prevented.


Inventors:
WATANABE TAKASHI
HASEGAWA KOICHI
Application Number:
JP35536297A
Publication Date:
July 09, 1999
Filing Date:
December 24, 1997
Export Citation:
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Assignee:
SHOWA DENKO KK
International Classes:
H01L33/30; (IPC1-7): H01L33/00
Attorney, Agent or Firm:
Yaguchi flat