Title:
ERROR DETECTING METHOD, ERROR DETECTION CIRCUIT OF MICROCOMPUTER AND MICROCOMPUTER SYSTEM
Document Type and Number:
Japanese Patent JP3652232
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an error detecting method and an error detection circuit of a microcomputer capable of judging failures by the free numbers and flexibly coping with an error and a microcomputer system.
SOLUTION: The error detecting method to perform similar arithmetic operations to each of two or more microcomputers to be mutually connected like a ring and having the same output expectation value is characterized that data as an arithmetic result is outputted from one microcomputer in the fixed direction, the data is inputted to another microcomputer adjacent to the microcomputer, an error signal is outputted in the opposite direction to the direction when output data and input data compared by the respective microcomputers are noncoincident, the error signal is inputted in the other microcomputer adjacent to one microcomputer and the microcomputer in which input/output of the error is generated is regarded as the error.
Inventors:
Tetsuya Hashimoto
Application Number:
JP2000296738A
Publication Date:
May 25, 2005
Filing Date:
September 28, 2000
Export Citation:
Assignee:
NEC Microsystems, Inc.
International Classes:
G06F9/38; G06F11/18; G06F11/30; G06F15/78; (IPC1-7): G06F11/18
Domestic Patent References:
| JP6149605A | ||||
| JP5216702A | ||||
| JP3103651U | ||||
| JP9244909A |
Attorney, Agent or Firm:
Aperture Muneaki
Previous Patent: PICTURE READ DEVICE AND METHOD FOR CONTROLLING THE SAME AND STORAGE MEDIUM
Next Patent: WIRELESS NETWORK SYSTEM
Next Patent: WIRELESS NETWORK SYSTEM