To provide a fail memory capable of creating accumulated data even when multiple bit device is used.

Before fail data from a memory tester 1 is inputted into a memory device 6, a logical sum of fail data with fail data at the identical address of one cycle previous time of the memory device 6 is calculated by an OR gate 12. The logical sum is made to be input data for an F/F 13. Output data of the F/F 13 is inputted to the memory device 6 when a three-state buffer 14 is in an enable condition and the data is fed back to the OR gate 12. Plural sets of the above circuits of which number of sets corresponds to the bit number of a memory IC are provided as data control sections 10-1-10-4.