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Patent Searching and Data


Title:
FAILURE ANALYZING METHOD OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH04243147
Kind Code:
A
Abstract:

PURPOSE: To make a failure analysis possible with the aid of an electron beam tester by making a hole in the insulating film in the upper part of a ground wiring to let a part of lower conductor layer come to the surface and thereafter by burying tungsten in the hole covered with the insulating film and onto the insulating film of the surface.

CONSTITUTION: A ground wiring 5 is formed by the use of a passivation film 6. By the use of a focused ion beam(FIB) apparatus, a hole 7 is made in the passivation film 6 and a metal film 8 is formed in the hole 7 and on the insulating film of the surface. Then, a hole is made in the metal film 8, the passivation film 6 is removed and a hole is made in a silicon nitride film 4. By the use of FIB, an oxide film is formed between the hole part and silicon nitride film 4, between the hole part and passivation film 6 and between the hole part and metal film 8 and in the top surface part of the metal film. The opening part is buried with tungsten and the electron beam of an electron beam tester is applied to the part. Thus, it is possible to measure potential without being affected by charging up through the passivation film 6.


Inventors:
KATO TOSHIHIRO
Application Number:
JP416991A
Publication Date:
August 31, 1992
Filing Date:
January 18, 1991
Export Citation:
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Assignee:
NEC CORP
International Classes:
G01R31/302; H01L21/66; G01R31/00; (IPC1-7): G01R31/00; H01L21/66
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)