Title:
FAILURE POINT MARKING METHOD
Document Type and Number:
Japanese Patent JP3671627
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To mark a failure point without judging the kinds of failure (line-to- ground fault, short circuit), failure phase and failure line.
SOLUTION: Phase current and voltage data are taken in from each terminal node of parallel two-line transmission system having a plurality of branches. Difference vectors VL and VR between 1L and 2L for voltage drop from the self terminal 1 and opposite terminal (n) to the front of the failure section, difference vectors VLU and VRu between 1L and 2L for voltage drop per unit length from the self terminal side node and opposite terminal side node to the failure point in the failure section, and difference vectors IIN and IIN' between 1L and 2L for the inflow current from the self terminal side node and opposite terminal side node are calculated. Using the calculated result and the distance (l) of the failure section, the distance x from the self terminal side node to the failure point is operated with x= Re{(-VL+VR+1(VRu)).(IIN +IIN')*/(VLu+VRu).-(IIN+IIN')*} and distance L from the self terminal, to the self terminal side node is added and the failure point distance X=L+x is marked.
Inventors:
Hitomi Otoguro
Funahashi Toshihisa
Mizuma Kaju
Funahashi Toshihisa
Mizuma Kaju
Application Number:
JP29972597A
Publication Date:
July 13, 2005
Filing Date:
October 31, 1997
Export Citation:
Assignee:
KABUSHIKI KAISHA MEIDENSHA
International Classes:
G01R31/08; (IPC1-7): G01R31/08
Domestic Patent References:
| JP8233895A | ||||
| JP9166639A |
Attorney, Agent or Firm:
Tsuyoshi Hashimoto
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