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Patent Searching and Data


Title:
FAULT DETECTOR OF WATCH DOG TIMER
Document Type and Number:
Japanese Patent JPS6055448
Kind Code:
A
Abstract:

PURPOSE: To improve the reliability fo a device by sending the fault detection signal of a watch dog timer when the value of the timer immediately before initialization is not within a specific level range.

CONSTITUTION: When an initializing signal A is not sent from a central processor 1A at specific intervals of time, the device outputs the fault detection signal B from the counter 1C of the watch dog timer 1B. The counted value D of the counter 1C is inputted to a digital input part 4A in the processor 1A and fetched in the processor 1A to decide whether the counted value is within the specific level range or not. When the counted value D is not within the specific level range, a fault pilot lamp (not shown in a figure) is lighted to detect the fault of the timer 1B and the fault of the processor 1A distinctively.


Inventors:
OOTA HIROSHI
Application Number:
JP16262383A
Publication Date:
March 30, 1985
Filing Date:
September 06, 1983
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
G06F11/30; G06F11/00; (IPC1-7): G06F11/30
Attorney, Agent or Firm:
Norio Ishii