Title:
FAULT PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JP3042034
Kind Code:
B2
Abstract:
PURPOSE: To prevent a system from shutting off when a memory error is fixedly generated during the execution of a restart processing program on a singlet central processing system such as an exchange.
CONSTITUTION: A memory error measurement counter 5, an OR circuit 6 inputting the OR output between a power-on reset signal and a multimemory error signal to a flip-flop 3, and an OR circuit 7 to be inputted to a restart control part 2 are provided on a fault processing part, and the memory error measurement counter 5 is counter up while using the memory error generation signal to be detected every time a memory error is generated as a clock. By a multimemory error signal to be outputted when the constant number of times of memory errors are generated, turning on a restart register and starting a start control part 2 are notified. By receiving this multimemory error signal, the start control part 2 recognizes that the power on bit is turned on, thereby executing the restart procedure at the time of turning on power supply.
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Inventors:
Kenji Fujisono
Youzo Iki
Youzo Iki
Application Number:
JP15208191A
Publication Date:
May 15, 2000
Filing Date:
June 25, 1991
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F11/14; H04M3/22; H04Q3/545; H04Q3/58; (IPC1-7): H04Q3/545; G06F11/14; H04M3/22; H04Q3/58
Domestic Patent References:
| JP59153249A | ||||
| JP583493A | ||||
| JP53114326A | ||||
| JP63638A | ||||
| JP1181295A |
Attorney, Agent or Firm:
Teiichi Igeta