Title:
フィードバックラッチ回路
Document Type and Number:
Japanese Patent JP6430667
Kind Code:
B2
Abstract:
A MOS device includes a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C. The first latch is configured to output Q, where the output Q is a function of CF, IF, and IC, and the latch feedback F is a function of the output Q. The first latch may include a first set of transistors stacked in series in which the first set of transistors includes at least five transistors. The MOS device may further include a second latch coupled to the first latch. The second latch may be configured as a latch in a scan mode and as a pulse latch in a functional mode. The first latch may operate as a master latch and the second latch may operate as a slave latch during the scan mode.
Inventors:
Yeah, Ji
Doan, Jenyu
Dillen, Stephen James
Datta, Animesh
Doan, Jenyu
Dillen, Stephen James
Datta, Animesh
Application Number:
JP2017564125A
Publication Date:
November 28, 2018
Filing Date:
March 31, 2016
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
H03K3/037; H03K3/3562
Domestic Patent References:
| JP61292414A | ||||
| JP49044655A |
Foreign References:
| US6791387 | ||||
| US7977976 |
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Morisezo Iseki
Takashi Okada
Yoshihiro Fukuhara
Morisezo Iseki
Takashi Okada
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