Title:
FERRODIELECTRIC MEMORY AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP3833887
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the variety or difference in conversion of patterns, accompanying lithography or minute processing, furthermore to minimize its influence on the polarization quantity of a capacitor, and to attain minuteness, high integration and improve the reliability.
SOLUTION: This ferrodielectric memory, comprising a ladder structure, is provided with a first plug which is connected to one of source and drain regions 106 of a transistor formed on an Si substrate 100, a second plug connected to another of the source and drain regions 106, a first capacitor electrode 115 connected to the first plug and formed into a block form, having two capacitor planes which are vertical to the channel direction, a ferrodielectric substance film 116 formed on the capacitor plane of the first capacitor electrode 115, and a second capacitor electrode 117 connected to the second plug and formed on the capacitor plane of the first capacitor electrode 115, while interlaying the ferrodielectric substance film 116 between them.
Inventors:
Imai Kataro
Koji Yamakawa
Koji Yamakawa
Application Number:
JP2000330619A
Publication Date:
October 18, 2006
Filing Date:
October 30, 2000
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L27/105; H01L21/8246; H01L27/115; H01L29/76; H01L29/94; H01L21/02; (IPC1-7): H01L27/105
Domestic Patent References:
| JP10255483A | ||||
| JP2000243921A | ||||
| JP9017972A |
Attorney, Agent or Firm:
Takehiko Suzue
Sadao Muramatsu
Atsushi Tsuboi
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai
Sadao Muramatsu
Atsushi Tsuboi
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai