To provide a reliable process for achieving selectivity for selectively etching spacer/side wall material on fin against spacer/side wall material on a gate stack of finFET structure in an integrated circuit.
A spacer material is deposited in conformal manner on both fin and gate stack. Inclined impurity injection is performed almost parallel to the gate stack so that only the spacer material deposited on the fin is selectively damaged. Thus, such finFET is provided as covers a part of fin of the semiconductor material formed on a substrate and contains a spacer having substantially uniform profile along the length of the gate stack. By a damage caused by inclined injection, the spacer material on the fin can be so etched as has a higher selectivity than the spacer material on the gate stack.
FALTERMEIER JONATHAN E
BASKER VEERARAGHAVAN S
DORIS BRUCE B
| JP2008277416A | 2008-11-13 | |||
| JP2009021456A | 2009-01-29 | |||
| JP2009503893A | 2009-01-29 |
Tasaichi Tanae
Yoshihiro City
Next Patent: LASER DIODE STRUCTURE WITH TEMPERATURE-CONTROLLED BEAM SHAPING ELEMENT AND METHOD FOR GAS DETECTION ...