Title:
FLIP-FLOP CIRCUIT AND MEMORY USING THE SAME
Document Type and Number:
Japanese Patent JPH06180990
Kind Code:
A
Abstract:
PURPOSE: To perform the initialization of a flip-flop circuit and memory at the time other than when a power supply is connected thereto, by using simple structure and small layout area.
CONSTITUTION: A flip-flop circuit is constituted of inverters 11, 12 in which the other outputs are connected to each other, and these outputs are led to the outside through transistors Q1, Q2 for transmission use for control. The current amplification factors of the transistors Q1, Q2 are set at a different value from each other. In order to do so, the ratio of the gate width to the gate length of both transistors Q1, Q2 may be changed.
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Inventors:
ISHII HIROSHI
Application Number:
JP35192992A
Publication Date:
June 28, 1994
Filing Date:
December 09, 1992
Export Citation:
Assignee:
NEC CORP
International Classes:
G11C11/41; H01L21/8244; H01L27/11; (IPC1-7): G11C11/41; H01L27/11
Domestic Patent References:
| JPS5164838A | 1976-06-04 | |||
| JPS62231492A | 1987-10-12 |
Attorney, Agent or Firm:
Yanagi Kawa Shin