Title:
【発明の名称】メモリアクセス方式
Document Type and Number:
Japanese Patent JP2999869
Kind Code:
B2
Abstract:
A memory circuit includes an input selector for receiving input data serially at an interval of a period T and outputting the input data and an address counter for generating first address data sequentially at an interval of a having period 2T and second address data sequentially at an interval having period 2T. The second address data is delayed a period T from the first address data. The memory circuit of the present invention further includes two memory blocks coupled to the input selector and address counter. One memory block stores even numbered input data in response to the first address data and outputs them at the interval of the period 2T. The other memory block stores odd numbered input data in response to the second address data and outputs them at the interval of the period 2T.
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Inventors:
Yasunori Sato
Shosaku Tsukakoshi
Yoshio Sakata
Shosaku Tsukakoshi
Yoshio Sakata
Application Number:
JP30020291A
Publication Date:
January 17, 2000
Filing Date:
November 15, 1991
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
G11C11/41; G11C7/00; (IPC1-7): G11C11/41
Domestic Patent References:
| JP376094A |
Attorney, Agent or Firm:
Yasunari Kakimoto