Title:
FLIP-FLOP CIRCUIT, SHIFT REGISTER CIRCUIT, SERIAL/PARALLEL CONVERTING CIRCUIT AND PARALLEL/SERIAL CONVERTING CIRCUIT
Document Type and Number:
Japanese Patent JP3586026
Kind Code:
B2
Abstract:
PURPOSE: To suppress the power consumption of the flip-flop circuit and to hardly generate malfunction by enlarging an output amplitude.
CONSTITUTION: The power consumption is reduced by using a series gate type ECL for the master latch of the flip-flop circuit. Series gating is not used for respective gates CR5, CR7 and CR9 at a slave latch but the output amplitude is enlarged by using an ECL parallelly connecting transistors.
Inventors:
Yasushi Hayakawa
Application Number:
JP324396A
Publication Date:
November 10, 2004
Filing Date:
January 11, 1996
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G11C19/28; H03K3/289; H03M9/00; H03K3/286; (IPC1-7): H03K3/289; G02B1/10; H03K3/286; H03M9/00
Domestic Patent References:
| JP2036610A | ||||
| JP3022622A | ||||
| JP63086611A | ||||
| JP63366924A | ||||
| JP62159516A |
Attorney, Agent or Firm:
Shigeaki Yoshida
Yoshitake Hidetoshi
Takahiro Arita
Yoshitake Hidetoshi
Takahiro Arita