To provide a flip-flop circuit that reduces the total capacity of its clock system so as to suppress power consumption.

Inverters 1, 2 supply a clock ck to master and slave side transmission gates 4, 8 without using a clocked inverter for data latching, and an NMOS transistor(TR) 5 and a PMOS TR 6 whose drain voltage/source voltage is inversely connected to that of a conventional CMOS circuit latch data when the transmission gates 4, 8 are open. Thus, the total capacity of the clock system can be reduced so as to suppress the power consumption.