PURPOSE: To reduce the stray capacitance and to decrease the delay or deterioration in a clock signal by adopting the constitution such that no other transistor(TR) is connected in parallel with a TR controlled by a clock signal.

CONSTITUTION: A set/reset TR being connected in parallel with a clock TR 1 is eliminated, TRs 61, 62 are connected in series with TRs 12, 13 forming a data input TR pair in a master circuit 55 and TRs 63, 64 are connected in parallel with a series circuit comprising TRs 12, 61 and 13, 62. TRs 71, 72 are connected in series with TRs 22, 23 forming a data input TR pair respectively and TRs 73, 74 are connected in parallel with a series circuit comprising the TRs 22, 71 and 23, 72. Furthermore, the TRs 61, 72 are driven by an inverted reset signal, inverse of R, the TRs 62, 71 are drive signal by an inverted set signal, inverse of S, the TRs 63, 74 are driven by a set signal S and the TRs 64, 73 are driven by a reset signal R respectively.