PURPOSE: To prevent set-up time from being prolonged by an influence to a master latch due to the state of a slave latch.

CONSTITUTION: While a clock C is logic '0', MOS transfer gates MP0 and NM0 are turned on, and data from a data input terminal D is fetched through an inverter INV 0 into the inside of the latch. When the clock C is turned to logic '1', MOS transfer gates (MP1 and MN1) are turned on, and the data is held by a positive feedback loop composed of the INV 1 and a gate NAND 0. The data is transmitted to the slave latch with an INV 2 as a buffer circuit, and the data is fetched into the match by turning on MOS transfer gates (MP2 and MN2) while the clock input C is logic '1'. While the clock C is logic '0', MOS transfer gates (MP3 and MN3) are turned on, and the data is held by a positive feedback loop composed of an INV 3 and a gate NAND 1. An output to a data output terminal Q is taken out from the preceding step of the INV 3 through an INV 4 so as to match a logic polarity with the data input terminal D.