Title:
FLOATING POINT MULTIPLICATION ACCUMULATION DEVICE
Document Type and Number:
Japanese Patent JP3803438
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve the system processing performance by limiting a data path within the specific bit width without connecting the higher order part of an addend to the multiplication result of a floating point multiplication accumulation(FMAC) device.
SOLUTION: The bits of a mantissa part 30 of numerical value C exceeding the range of a mantissa part 28 of the multiplication result (A×B) of both numerical value A and B of an FMAC device 20 are stored in a CHI register 32 and then stored in a CBUS register 36 used for bits of the mantissa 30 of the value C overlapping the range of the mantissa 28. A 1st shift unit 34 shifts the mantissa 30 to the left by the number of bits equivalent to the difference of exponents of both mantissas 28 and 30 and stores this bit position in the register 36. Then a 2nd shift unit 42 shifts the output of a head bit forecast unit 40 to the right by the number of bits equivalent to the difference of exponents of both mantissas 28 and 30 and outputs this shift result to an accumulation result output part 44. Then the bits stored in the register 32 are connected to the higher order bits of the output 44.
Inventors:
Samuel Dee Nafziger
Randal Earl. Hube
Randal Earl. Hube
Application Number:
JP30445196A
Publication Date:
August 02, 2006
Filing Date:
November 15, 1996
Export Citation:
Assignee:
HEWLETT-PACKARD COMPANY
International Classes:
G06F7/00; G06F17/10; G06F7/544; G06F7/76; (IPC1-7): G06F17/10; G06F7/00
Domestic Patent References:
| JP9146924A | ||||
| JP5233228A |
Attorney, Agent or Firm:
Next student Okada
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