FORMATION OF JUNCTION LAYER

Title:

FORMATION OF JUNCTION LAYER

Document Type and Number:

Japanese Patent JPS6190429

Kind Code:

A

Abstract:

PURPOSE:To enable low-temperature and short-time activation and shallow- junction formation by combining Si ion (S<+>) implantation with lamp annealing. CONSTITUTION:An SiO2 film is formed by 1,000Angstrom oxidation of the wafer surface of an N type Si substrate (3-6OMEGAcm), and a continuous amorphous region is formed on the Si substrate by multistep implantation of Si ion (Si<+>) through this oxide film on the basis of Formula (1). Next, boron ions (B<+>) are implanted to this amorphous region under conditions of implantation: 40keV, 3X10<15> ions/cm<2>; further, 10sec lamp annealing is carried out at a temperature range of 600-800 deg.C. Then, the boron ions (B<+>) are sufficiently activated, resulting in the formation of a shallow P<+> junction layer of approx. 0.1mum thickness.

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Inventors:

ONISHI SHIGEO
BIWA TETSUO
SHIMIZU HIROAKI

Application Number:

JP21215284A

Publication Date:

May 08, 1986

Filing Date:

October 09, 1984

Export Citation:

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Assignee:

SHARP KK

International Classes:

H01L21/26; H01L21/265; (IPC1-7): H01L21/265; H01L21/324

Attorney, Agent or Firm:

Sugiyama Takeshi

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