Title:
FORMATION OF RESISTOR
Document Type and Number:
Japanese Patent JP3283581
Kind Code:
B2
Abstract:
PURPOSE: To form a resistor suitable for MMIC by the method for formation of a resistor to be used for a semiconductor active layer.
CONSTITUTION: This resistor forming method is composed of a process in which a non-doped layer 1, the first impurity-doped layer 3 and the second impurity- doped layer 4 are grown sucessively on a compound semiconductor substrate 1, a process in which two electrodes 5a and 5b to be used to ohmic contact are formed leaving an interval on the second impurity-doped layer 4, and another process in which a resistance value is adjusted by selectively etching a part or the whole part of the second impurity-doped layer 4 located between the two electrodes 5a and 5b. Also, the growth of the non-doped layer 2, the first impurity-doped layer 3 and the second impurity-doped layer 4 is conducted simultaneously with the growth of the electron transit layer of a high electron mobility transistor, an electron feeding layer and a contact layer.
Inventors:
Hiroshi Mino
Application Number:
JP22903892A
Publication Date:
May 20, 2002
Filing Date:
August 28, 1992
Export Citation:
Assignee:
富士通株式会社
富士通カンタムデバイス株式会社
富士通カンタムデバイス株式会社
International Classes:
H01C17/06; H01C13/00; H01C17/24; H01L21/338; H01L21/822; H01L27/04; H01L29/778; H01L29/812; (IPC1-7): H01L27/04; H01C13/00; H01C17/24; H01L21/338; H01L21/822; H01L29/778; H01L29/812
Domestic Patent References:
| JP63158864A |
Attorney, Agent or Firm:
Junichi Yokoyama