PURPOSE: To obtain a frequency division signal with the frequency division ratio of a different series simultaneously with the hardware configuration as small as possible.

CONSTITUTION: A frequency division signal X whose frequency division ratio is 1/N is obtained from a prescribed clock signal CLK. A desired frequency division ratio 1/N is set to a 1st register 1. A bit detection circuit 4 detects a bit closest to the most significant bit giving a logical value '1' and gives the position of the detected bit to a coincidence detection circuit 6. A counter 5 counts the clock signal CLK to obtain a counted value C. An initial value '0' is given to a 2nd register 2. The coincidence detection circuit 6 compares the logical value of a bit at the location detected by the bit detection circuit 4 with the logical value of a bit at the subordinate location with respect to the counted value C and outputs a pulse with a prescribed width as a frequency division signal X when the coincidence of them is detected and adds the setting value 1/N to data of the 2nd register for the updation.