PURPOSE: To obtain an output signal having a duty ratio equal to that of an input signal by dividing the frequency of the input signal to 1/9.

CONSTITUTION: D flip-flops 11, 12, 13 use respectively an input signal as their drive source and the D flip-flop 11, 12 form a shift register A. Similarly, D flip-flops 14, 15, 16 use an inverse of the input signal (a) and the D flip-flops 14, 15 form a shift register B. A noninverting output signal of the D flip-flop 12 is fed to a data input terminal of the D flip-flop 16, and a noninverting output signal of the D flip-flop 15 is fed to a data input terminal of the D flip-flop 13. Each inverting output signal of the D flip-flops 13, 16 is fed to an AND gate 18. An output signal of the AND gate 18 is fed to the shift registers A, B. The period of the output signal of the AND gate 18 is a multiple of 9/2 of the period of the input signal (a). A DFF 17 formed to divide an output signal frequency of the AND gate 18 into 1/2 is used to obtain an output signal (b) whose duty ratio is equal to that of the input signal (a) and subject to 1/9 frequency division.