PURPOSE: To provide the 1/3 frequency divider circuit in which no delay element is required, the mount scale is reduced and monolithic processing is easily attained when a 1/3 frequency division clock whose duty ratio is 1:1 is obtained.

CONSTITUTION: The frequency divider circuit is provided with an exclusive OR gate 1 whose input terminal is connected to a clock signal input terminal, a 1st flip-flop 2 whose clock input terminal is connected to an output terminal of the exclusive OR gate, and a 2nd flip-flop 3 whose data input terminal is connected to an inverting output terminal of the 1st flip-flop 2, whose output terminal is connected to a data input terminal of the 1st flip-flop 2 and is used for a frequency division output terminal.