PURPOSE: To realize a small change in a frequency of an output pulse train in a 1/N frequency divider circuit without much increase in the repeating frequency of the input pulse train and much increase in a frequency division setting value N.

CONSTITUTION: A 1st latch 103 storing a frequency division setting number N, a 1st counter 105 to count a pulse number of an oscillation output 201 and a 1st comparator are used to obtain a frequency division output 202. The frequency division circuit is provided with a decoder 108 comprising a PROM storing in advance plural frequency division patterns and with a 2nd counter 107 to count a pulse number of the frequency division output 202, and each bit of one set of frequency division pattern data selected by a 2nd latch is given to the 1st comparator 104 as a decode output 206. The 1st comparator 104 discriminates the frequency division setting value N to be tentatively larger so long as the 1st comparator 104 receives a decode output 206 as a level 1.