Title:
FREQUENCY DIVIDER CIRCUIT
Document Type and Number:
Japanese Patent JPH07307664
Kind Code:
A
Abstract:
PURPOSE: To obtain an extremely high or low frequency-division coefficient by adding an input terminal invalidating this circuit to one cell. CONSTITUTION: A cell C1 receives a signal FI1 , and a second output terminal SO1 supplies a signal with the same frequencies as those of a final active cell output frequency signal. A terminal O4 of a final cell CD4 is connected with a ground, and a terminal SI4 is connected with a power supply terminal VCC, and the cell CD4 is turned into a level 1 logic. Finally, a frequency dividing circuit output terminal is connected with a circuit 5, and an output signal duty cycle is increased. Then, for example, when the number of frequency-division is less than 16, a programming bit PGM5 is fixed to 0, and a terminal SI3 of a cell CD3 is always set as a logical level 1. Also, when the number of frequency-vision is 8-15, a bit PGM4 is fixed to 1, the output terminal of an OR gate OR1 is turned into 1, and the other programming bits are selected as the function of the necessary number of frequency-division. Moreover, when the number of frequency-division is less than 8, the output of a gate 0R3 is turned into 0, and a terminal SI2 of a cell CD2 is turned into 1.
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Inventors:
DUFOUR YVES (FR)
Application Number:
JP10866395A
Publication Date:
November 21, 1995
Filing Date:
May 02, 1995
Export Citation:
Assignee:
KONINKL PHILIPS ELECTRONICS NV (NL)
International Classes:
H03K3/021; H03K23/64; H03K3/2885; H03K23/66; H03L7/18; (IPC1-7): H03K23/64
Attorney, Agent or Firm:
Akihide Sugimura (5 outside)