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Title:
同期出力を有する周波数分周器
Document Type and Number:
Japanese Patent JP2012521669
Kind Code:
A
Abstract:
A synchronized frequency divider that can divide a clock signal in frequency and provide differential output signals having good signal characteristics is described. In one exemplary design, the synchronized frequency divider includes a single-ended frequency divider and a synchronization circuit. The single-ended frequency divider divides the clock signal in frequency and provides first and second single-ended signals, which may be complementary signals having timing skew. The synchronization circuit resamples the first and second single-ended signals based on the clock signal and provides differential output signals having reduced timing skew. In one exemplary design, the synchronization circuit includes first and second switches and first and second inverters. The first switch and the first inverter form a first sample-and-hold circuit or a first latch that resamples the first single-ended signal. The second switch and the second inverter form a second sample-and-hold circuit or a second latch that resamples the second single-ended signal.

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Inventors:
Chao, Dong Jiang
Boss, frederick
Application Number:
JP2012500972A
Publication Date:
September 13, 2012
Filing Date:
March 18, 2010
Export Citation:
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Assignee:
QUALCOMM INCORPORATED
International Classes:
H03K23/42; H03K19/096; H04B1/40
Domestic Patent References:
JP2000049594A2000-02-18
JP2009290775A2009-12-10
JPH01202923A1989-08-15
JP2007243617A2007-09-20
JPH0738423A1995-02-07
JP2000049594A2000-02-18
Foreign References:
US20080186063A12008-08-07
US7012956B12006-03-14
US20080164927A12008-07-10
US20070109019A12007-05-17
EP0926833A11999-06-30
US20080186063A12008-08-07
Attorney, Agent or Firm:
Kurata Masatoshi
Takakura Shigeo
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori



 
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