PURPOSE: To obtain the frequency divider without being affected by the frequency and duty factor of a signal to be frequency divided.

CONSTITUTION: A shift register 14 is composed by connecting D flip-flops 1a-5a (only the output of the D flip-flop 5a is non true value side data) to be operated synchronously with the rise of a clock CP in the shape of a loop, and a shift register 15 is composed by connecting D flip-flops 1b-5b (only the output of the D flip-flop 5b is non true value side data) to be operated synchronously with the fall of the clock in the shape of a loop. The exclusive OR of outputs from the D flip-flops la and 2a in the shift register 14 is connected to a set signal input terminal S of an R-S latch 19, and the exclusive OR of outputs from the D flip-flops 3b and 4b in the shift register 15 is connected to a reset signal input terminal R of the R-S latch. The out put of this R-S latch 19 is outputted from a frequency dividing signal output terminal 13. Therefore, the frequency divider is not affected by the frequency or duty factor of the signal to be frequency divided.