To secure almost the same duty ratio for the frequency divided output signals despite the odd frequency division and also to attain a fast frequency dividing operation.

A D flip-flop 11 operates at the rise of a clock CK and sets its output signal Q1 at a high level. Then the flip-flop 11 is reset and the signal Q1 is set at a low level when the clock CK is set at a low level and the output of an OR circuit 16 is also set at a low level. Thus the signal Q1 is used as a 3 frequency dividing signal of the clock CK. A D flip-flop 12 is controlled in an operable state and a reset state by the signal Q1, and the states of both flip-flop 11 and circuit 16 are controlled by an output signal Q2 of the flip-flop 12. Thus almost the same duty ratio is secured for the 3 frequency dividing signals. Furthermore, the frequency dividing speed is increased owing to the direct use of the clock CK.