PURPOSE: To prevent a decrease in current consumption and a delay in an operation time and to reduce a maximum logic stage number so as to attain low voltage operation by dispersing a circuit element into plural D latches into the frequency dividing circuit.

CONSTITUTION: A basic circuit section 1 consists of a frequency dividing circuit composed of dual loops being a loop of D latches 11-14 and a loop of D latches 11-16. The latches 11-14 generate a pulse signal whose period consists of 4-6 clocks. An OR between the output of the latch 14 and the output of an expansion circuit section 2 is inputted to the latch 15, from which a modified pulse signal is generated. Moreover, an OR between the output of the latch 15 and the output of an expansion circuit section 3 is inputted to the latch 16, from which a modified pulse signal is generated. Then a pulse signal whose one period consists of 17 clocks is generated at the output X13 of a D latch 20 by the operation of each section.