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Title:
FREQUENCY DIVISION CIRCUIT
Document Type and Number:
Japanese Patent JPS61192126
Kind Code:
A
Abstract:

PURPOSE: To divide a clock to N/2 in frequency with comparatively simple constitution by acting a counter circuit operated by an inverted clock without multiplying a fundamental clock and a counter circuit operated by a non- inverting clock.

CONSTITUTION: The counter circuit 1 is actuated by a fundamental clock (a) and the counter circuit 2 is operated by using a clock (b) inverted by an inverter 3. The counter circuits 1, 2 are formed as ternary counters and a counter '6' is set by a preset switch 5. Outputs (c, e) are shifted by a half clock of the fundamental clock. Outputs (c, e) shifted by the half clock are fed respectively to flip-flops 6, 7 to form outputs (f, g). Then the outputs (f, g) are fed to an exclusive OR gate 8 to obtain an exclusive OR output, and the inverted signal (h) and the signal (f) are ANDed (9) to obtain a frequency division output (i). This corresponds to 5/2 frequency division of the fundamental block (a).


Inventors:
IKUHARA HIDEYUKI
Application Number:
JP3202985A
Publication Date:
August 26, 1986
Filing Date:
February 20, 1985
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03K23/66; H03K21/00; H03K23/68; (IPC1-7): H03K23/66; H03K23/68
Attorney, Agent or Firm:
Akira Kobiji (2 outside)



 
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