PURPOSE: To generate a frequency division clock signal being the same phase of the same frequency by dividing a clock signal.

CONSTITUTION: Frequency division conters 1A1,..., 1NN invert every time a clock MCK rises and frequency division clock signal being the same phase of the same frequency are generated. The outputs of the frequency division counters 1A1,... 1NN are inputted in a gate circuit 21 constituted of an AND or an OR circuit, and when the phases of the outputs of the frequency division counters are unmatched, the output of the gate circuit 21 is fixed to either one state of an H level or an L level and the unmatching of the phases is detected. When the unmatching of the phases is detected, a self correction circuit 41 initializes all the counters 1A1,..., 1NN and matches the phase of the frequency division counters. The output of one of the frequency division counter is supplied to all the frequency counters via a buffer circuit 31 and the phases of the frequency division clocks can be matched.