Title:
FREQUENCY SYNTHESIZER
Document Type and Number:
Japanese Patent JP3161970
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide low-noise high resolution, to simplify the circuit configuration and to easily make a circuit into an IC by coupling the output of a PLL and the output of a delay detector and using the result as the control voltage of a VCO.
SOLUTION: The frequency of an oscillated output voltage V(t) of a VCO 10 is locked at a target value by a PLL 30. In this case, an output voltage Vout 1 of a delay detector 20 and an output voltage Vout of the PLL circuit 30 are coupled by a coupling circuit 40 and a voltage Vout 3 provided as a result is used as the control voltage of the VCO 10. Therefore, the output voltage Vout 1 of the delay detector 20 is utilized for generating the control voltage of the VCO 10 and without using a lot of PLL or high-Q VCO, the frequency synthesizer of low noise and high resolution can be provided.
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Inventors:
Kenichi Kawano
Shunji Ono
Shunji Ono
Application Number:
JP13640996A
Publication Date:
April 25, 2001
Filing Date:
May 30, 1996
Export Citation:
Assignee:
Japan Radio Co., Ltd.
International Classes:
H03L7/18; H03L7/22; (IPC1-7): H03L7/18
Domestic Patent References:
| JP6152393A | ||||
| JP1198826A | ||||
| JP3140030A | ||||
| JP8195676A |
Attorney, Agent or Firm:
Kenji Yoshida (2 outside)