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Title:
FULL-WAVE RECTIFYING DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPS5479551
Kind Code:
A
Abstract:

PURPOSE: To simplity IC-implementation by providing two emitter-follower circuits with emitters connected to a common load.

CONSTITUTION: Transistors TR1 and TR2 constitute emitter follower circuits with common emitter load resistance R1 respectively. Although applying an AC signal to the premary side of transformer T1 applies a DC bias and the AC signal superposed each other to bases of TR1 and TR2, the DC bias component of them allows 2xVBE to be supplied to the emitter since the base potential is 3xVBE, and the signal component allows the emitter potential not to fall below 2xVBE but to rise. As a result, the emitter varies with only a half the positive signal component, so that a rectified waveform will appear at the emitter. In addition, since out-of-phase signal waveforms are applied to TR1 and TR2, the emitter potential is made to rise alternately when the signal has positive amplitude, so that its full- wave rectified waveform will appear at the emitter.


Inventors:
MORI EIZOU
Application Number:
JP14763777A
Publication Date:
June 25, 1979
Filing Date:
December 07, 1977
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03D1/18; H02M7/21; (IPC1-7): H03D1/18



 
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