PURPOSE: To reduce a test time with a greater test speed, by generating a test input pattern using an exclusive OR between a fixed value data output per specified cycle and a timing pulse having the same cycle as that of the data output and a width narrower than the data output.

CONSTITUTION: In the generation of an input pattern, a test input pattern is generated using an exclusive OR between a data output taking a value binary and determined at each specified cycle and a timing pulse having the same cycle as, and a width narrower than, the data output. As the data output and the timing pulse are both binary and the width of the timing pulse is narrower than that of the data output, there is sure to be a part having the data output level coinciding with the timing pulse level and that having none within one cycle. Thus, two different DC levels can be generated within one cycle by obtaining an exclusive OR between the these parts, thereby enabling a reduction in the test time.