PURPOSE: To increase the degree of designing freedom of the contact with a gate signal interconnection of a logic circuit by a method wherein the united structure of a gate electrode part and a gate interconnection part of a fundamental cell is formed in a ring shape and a ring-shaped structure in which one part of the gate interconnection part used to come into contact with an interconnection metal crosses many interconnection lattices perpendicularly is formed.

CONSTITUTION: A fundamental cell is provided with X-direction interconnection lattices 1a to 1d and Y-direction interconnection lattices 2a to 2e. Gate electrode parts 3a of a MOS transistor are formed on source-drain diffusion layers 4a to 4c of the MOS transistor. Gate interconnections 3b are formed so as to have a width capable of coming into contact with a gate signal interconnection metal; they are passed on the Y-direction lattices 2a, 2e crossing a plurality of X-direction interconnection lattices 1a to 1d perpendicularly; they are formed to be U-shaped; they are connected to both ends at the upper part and the lower part of the gate electrode parts 3a; the gate interconnection parts 3b and the gate electrode parts 3a form a ring-shaped structure. Thereby, the degree of designing freedom of the contact with a gate signal interconnection layer of a logic circuit can be increased.