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Title:
GLOBAL ASYNCHRONOUS COMMUNICATION ARCHITECTURE OF SYSTEM ON-CHIP
Document Type and Number:
Japanese Patent JP2006254449
Kind Code:
A
Abstract:

To develop a new data transmission method in a global asynchronous network on-chip, capable of containing an element used for synchronous logic and/or an element used for asynchronous logic, and to develop a device that is usable for the method.

The method is used for transferring data on the network on-chip by using especially an asynchronous "send/accept" type protocol, regarding the field of network on-chip (NoC). The network on-chip is used for executing the method.


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Inventors:
CLERMIDY FABIEN
VIVET PASCAL
BEIGNE EDITH
Application Number:
JP2006062181A
Publication Date:
September 21, 2006
Filing Date:
March 08, 2006
Export Citation:
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Assignee:
COMMISSARIAT ENERGIE ATOMIQUE
International Classes:
H04L12/54
Domestic Patent References:
JPH08508599A1996-09-10
JPH08508599A1996-09-10
Other References:
JPN6010048888, Ｅｖｇｅｎｙ　Ｂｏｌｏｔｉｎ　ｅｔ．ａｌ．, "ＱＮｏＣ：　ＱｏＳ　ａｒｃｈｉｔｅｃｔｕｒｅ　ａｎｄ　ｄｅｓｉｇｎ　ｐｒｏｃｅｓｓ　ｆｏｒ　ｎｅｔｗｏｒｋ　ｏｎ　ｃｈｉｐ", Ｊｏｕｒｎａｌ　ｏｆ　Ｓｙｓｔｅｍｓ　Ａｒｃｈｉｔｅｃｔｕｒｅ，　Ｖｏｌｕｍｅ　５０，　Ｉｓｓｕｅｓ　２−３, 200402, Ｅｌｓｅｖｉｅｒ　Ｂ．Ｖ．, ｐ．１０５〜１２８
JPN6010048889, Ｋｕｍａｒ，　Ｓ．　ｅｔ．ａｌ．, "Ａ　ｎｅｔｗｏｒｋ　ｏｎ　ｃｈｉｐ　ａｒｃｈｉｔｅｃｔｕｒｅ　ａｎｄ　ｄｅｓｉｇｎ　ｍｅｔｈｏｄｏｌｏｇｙ", ＶＬＳＩ，　２００２．　Ｐｒｏｃｅｅｄｉｎｇｓ．　ＩＥＥＥ　Ｃｏｍｐｕｔｅｒ　Ｓｏｃｉｅｔｙ　Ａｎｎｕａｌ　Ｓｙｍｐｏｓｉｕｍ　ｏｎ, 20020807, ｐ．１０５〜１１２
JPN7010002663, Ｔ　Ｆｅｌｉｃｉｊａｎ, "Ｑｕａｌｉｔｙ−ｏｆ−Ｓｅｒｖｉｃｅ　（ＱｏＳ）　ｆｏｒ　Ａｓｙｎｃｈｒｏｎｏｕｓ　Ｏｎ−Ｃｈｉｐ　Ｎｅｔｗｏｒｋｓ", Ａ　ｔｈｅｓｉｓ　ｓｕｂｍｉｔｔｅｄ　ｔｏ　ｔｈｅ　Ｕｎｉｖｅｒｓｉｔｙ　ｏｆ　Ｍａｎｃｈｅｓｔｅｒｆｏｒ　ｔｈｅ　ｄｅｇｒｅｅ　ｏｆ　Ｄｏｃｔｏｒ　ｏｆ　Ｐｈｉｌｏｓｏｐｈｙ　ｉｎ　ｔｈｅＦａｃｕｌ, 2004
Attorney, Agent or Firm:
Sonoda Yoshitaka
Kobayashi Yoshinori



 
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