COMMUNICATION NODE ARCHITECTURE IN GLOBAL ASYNCHRONOUS NETWORK ON-CHIP SYSTEM

Japanese Patent JP2006254450

A

To develop a new global asynchronous network on-chip structure having an element for managing the internal data transmission, without using clocks, especially those equipped with nodes.

A method for transmitting elements using "send/accept" asynchronous communication protocol in a network related to the field of network on-chip (NoC) is considered. At least one node in the network is operated without internal clock, and the node determines the transfer hierarchy between two data packets routed to the same output, based on the priority channel information related to each data packet.

JP2002135511	COMMUNICATION TERMINAL AND REPEATER
JPH0752887	INDUSTRIAL APPLICABILITY: A method for managing a center key in a star-shaped system.
JP3814991	ELECTRONIC MAIL EDITING DEVICE AND STORAGE MEDIUM

BEIGNE EDITH
VIVET PASCAL
RENAUDIN MARC
QUARTANA JEROME

JP2006062182A

September 21, 2006

March 08, 2006

Click for automatic bibliography generation  

COMMISSARIAT ENERGIE ATOMIQUE
CENTRE NAT RECH SCIENT
INST NAT POLYTECH GRENOBLE

H04L12/54; H04L29/06

CSNG200200088010, 小西隆介　他, "非同期式動的再構成可能ＬＳＩによる自己複製回路", 信学技報　Ｖｏｌ．１００　Ｎｏ．４７５, 20001123, ｐ．５９〜６４

Sonoda Yoshitaka
Kobayashi Yoshinori

Previous Patent: GLOBAL ASYNCHRONOUS COMMUNICATION ARCHITECTURE OF SYSTEM ON-CHIP

Next Patent: FREQUENCY DIVIDER WITH SLIP