Title:
ハイブリッド浮動小数点フォーマットのドット積累算命令を有するグラフィックスプロセッサ及びグラフィックス処理ユニット
Document Type and Number:
Japanese Patent JP7107482
Kind Code:
B2
Abstract:
Methods and apparatus relating to memory controller techniques. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, and a processor communicatively coupled to the cache memory and the high-bandwidth memory, the processor to manage data transfer between the cache memory and the high-bandwidth memory for memory access operations directed to the high-bandwidth memory. Other embodiments are also disclosed and claimed.
Inventors:
Mayurin, Subra maniam
Mawaha, Shubra
Garg, Ashtosh
Pal, Splatim
Parla, George
Gram, Chandra
George, Varghese
Starkey, Darin
Ruay, Guei-Yuan
Mawaha, Shubra
Garg, Ashtosh
Pal, Splatim
Parla, George
Gram, Chandra
George, Varghese
Starkey, Darin
Ruay, Guei-Yuan
Application Number:
JP2021544339A
Publication Date:
July 27, 2022
Filing Date:
March 14, 2020
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G06T15/00; G06F9/302; G06F9/345; G06F9/38; G06T1/20
Foreign References:
| US20190079767 |
Attorney, Agent or Firm:
Longhua International Patent Service Corporation
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